1. Field of the Invention
The present invention relates in general to a packaging substrate. More specifically, it relates to a chip-packaging substrate capable of reducing damage to the substrate during packaging.
2. Description of the Related Art
Ball Grid Array (hereinafter referred to as BGA) packaging is widely applied to package the integrated circuits of chip sets or graphic chips, etc. The BGA packaging has a plurality of tin balls provided onto the bottom surface of a substrate and arranged in a form of an array. The balls serve as the leads or pins (conductive media) between a chip (or IC) and a circuit board, replacing the conventional lead frames. The BGA packaging can provide not only more pins but also larger space between every two adjacent pins than that of conventional packaging, under the same size of substrate. Compared with the conventional QFP, with pin number up to 304 but whose pins are easily bent or twisted, BGA packaging is not subject to this issue. In addition, BGA packaging provides superior heat dissipation and electrical conductivity by providing shorter conducting paths between the chip and the circuit board.
According to the raw material of the substrate, BGA substrates are divided into three categories: Plastic BGA (PBGA), Metal BGA (MBGA), and Tape BGA (TBGA). The PBGA substrate is made of organic materials such as compounds of BT resin and glass fiber. It is the most popular BGA substrate in the packaging industry.
FIG. 1A shows a top view of a PBGA substrate. The PBGA substrate in FIG. 1A has four units, in the form of a 1×4 array, for packaging 4 chips. The packaging units of a PBGA substrate can also be arranged in the form of an n×m (n and m≧1) array for specific requirement. FIG. 1B shows an enlarged view of one unit 100 of the PBGA substrate. In FIG. 1B, the unit 100 comprises a rectangular packaging portion 102, a rectangular frame portion 104 enclosing the packaging portion 102 so that a gap exists between the outer edge of the packaging portion 102 and the inner edge of the frame portion 104, and four connecting portions (106a˜106d) respectively provided to connect the four corner regions at the outer edge of the packaging portion 102 with the four corner regions at the inner edge of the frame portion 104. All the four connecting portions (106a˜106d) are substantially L-shaped and connect the packaging portion 102 and the frame portion 104 to form the main body of the unit 100.
A first circuit layer (for example, a copper layer not shown in FIG. 1B) is provided on the top surface of the unit 100. An isolating paint covers the first circuit layer, only revealing a portion of the first circuit layer at some specific positions. A second circuit layer (for example, a copper layer not shown in FIG. 1B) is provided on the bottom surface of the unit 100. An isolating paint also covers the second circuit layer, only revealing a portion of the second circuit layer at some specific positions. The first and second circuit layers have corresponding connections electrically.
The main process for packaging a chip using the PBGA unit 100 comprises the steps of: (1) Assembly, (2) Molding, (3) Ball grid implantation, and (4) Singulation, as illustrated in FIG. 2.
Assembly mounts a die (chip) cut from a wafer to the top surface of the packaging portion 102 of the PBGA unit 100, and then provides gold bonding wires to electrically connect the die with the revealing first circuit layer.
Molding encapsulates the die mounted in the packaging portion 102, using a packaging body in conjunction with plastic (or glue) material.
Ball grid implantation forms a plurality of conductive balls, arranged in the form of an array, on the second circuit layer on the bottom surface of the PBGA unit 100.
Singulation separates the frame portion 104 and the encapsulated packaging portion 102 by destroying the connecting portions 106a˜106d using press machine or cutting apparatus.
The first, second, third and fourth connecting portions (106a˜106d) are of the same dimensions and sizes. Using the second connecting portion 106b as an example, each of the two branches of the L-shaped second connecting portion 106b extends a distance of L1 along the adjacent inner edge of the frame portion 104.
For the PBGA substrate with packaging area of 40 mm×40 mm (the area of the packaging portion 102), the distance of L1 is about 3 mm to 4 mm. The distance of L1 is long enough that the distance (L2) of the gap slot 108 becomes smaller. Consequently, damage such as cracks and chip-out will easily occur on the packaging portion 102 when carrying out the singulation process.
Additionally, no copper layer is formed on the top surface of the frame portion 104 and therefore the surfaces of the first circuit layer (formed on the packaging portion 102) and that of the frame portion 104 are not flush. The height difference between the surfaces of the packaging portion 102 and the frame portion 104 will cause glue overflow (disfiguring the outlook of the encapsulated chip) or pressing damage to packaging portion 102 of the PBGA substrate when molding.